Digital computers process a variety of diverse types of programs, with each program including a series of instructions that enable the computer to perform specific operations in connection with specific elements of data. A variety of types of processors are available for use in digital computer systems, with each type of processor being constructed in accordance with an architecture which describes, inter alia, the set of instructions that a processor constructed in accordance with the architecture is expected to execute, the format(s) of the various instructions, the types and formats of data which may be processed, definitions for various registers that may be used during instruction processing, how information in the computer's memory will be accessed and how a processor constructed in accordance with the architecture is to handle exception conditions which may be detected during instruction processing.
It is often desirable to enable one type of processor, as an "emulated processor," to be emulated by another type of processor, as a "host processor." A host processor generally emulates an emulated processor by processing programs which have been written for the emulated processor, to generate an output that effectively corresponds to the output that would be generated by the emulated processor. Generally, emulation is accomplished by translating a program generated for execution by an emulated processor (an "original" program) into a program which may be processed by a host processor (a "translated" program). This translation process may include, for example, generating from instructions and other elements of the original program, instructions and other elements which are based on the host processor's architecture thereby to provide the translated program. The translation may be performed by, for example, the host processor itself, by another processor in the same computer system or by another computer system and made available to the host processor which is to process the program, under control of a translation program. In performing the translation, each instruction or sequences or various groups of instructions in the original program (that is, the program based on the emulated processor's architecture) may be translated into one or a series or group of instructions for processing by the host processor. The translation process is typically performed for all or selected portions of an original program when the processor begins processing the original program, although it will be appreciated that an instruction or group of instructions of the original program may be translated as the processing proceeds. In addition, if the emulated processor's data formats are not directly useable by the host processor, the data may be processed to convert it from the emulated processor's formats to formats usable by the host processor.
As noted above, an architectural definition includes a description of how a processor constructed in accordance with the architecture accesses information in the computer's memory. Normally, data is stored in a memory subsystem which includes a series of storage locations, each of which has the capacity to store an eight-bit byte of data, and which are associated with a corresponding series of successive address values. Typically, a processor can process items of data, each comprising, for example, one, two, four, eight and so forth, bytes (generally, quantities of 2.sup.n bytes, where "n" is an integer), and modern processor architectures typically require that the data items be stored in an "aligned" fashion. That is, the architectures require that two-byte data items be stored in memory locations that are accessed having addresses that are divisible by two, and that four-byte and eight-byte, data items be stored in memory locations that are accessed having addresses that are divisible by four. If a data item is not properly aligned, typically the memory subsystem or the processor would need to perform a series of operations, after the contents of one or more storage locations are retrieved during a retrieval operation, to reorganize the contents and extract the desired data item from the retrieved contents, or during a storage operation, to re-organize the data item and store it in one or more storage locations.
For processors constructed in accordance with such modem architectures, if a memory access were to make use of an address that is not properly aligned, typically an exception handler would be called to handle the operation. The exception handler may control the processor to perform a number of operations to enable the contents of a number of storage locations to be retrieved and the data item fabricated from portions of the retrieved contents, during a retrieval operation, or to disassemble various portions of the data item and store them in respective storage locations, in a storage operation. Alternatively, to avoid the significant amount of overhead which would be encountered in calling the exception handler, performing the remedial operations, and returning to the program, the exception handler may merely enable the processor to terminate the program which made use of the non-aligned address reference. To avoid either of these, typically compilers provide that data items are laid out in the memory to ensure that non-aligned references are avoided.
However, a number of older architectures, illustratively the Intel Corporation x86 family of microprocessors, which currently includes its 8086, 8088, 80286, 80386, 80486 and "Pentium.TM." lines of microprocessors, permit non-aligned references. A problem arises, however, if it is desired to enable a "host" processor, which is constructed according to one of the modern architectures which requires that memory accesses be aligned, to emulate an emulated processor which does not require such alignment, since a non-aligned reference may be encountered during such emulation.